This application is based upon and claims priority of Japanese Patent Application No. 2002-051929, filed on Feb. 27, 2002, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device having a layer structure with one semiconductor chip bonded to another, and a method for fabricating the semiconductor device.
2. Description of the Related Art
Recent years have seen semiconductor devices in a package structure with semiconductor chips being stacked in layers to increase packing density and a technique for layering semiconductor chips in the form of wafers. In this case, first, wires are formed on the elements of a wafer to ensure electrical connections with those semiconductor chips to be stacked thereon, and then the semiconductor chip are stacked on the wafer and bonded to the elements. The semiconductor chip to be bonded is connected to the wire formed on the wafer through the use of gold wires, solder bumps, or gold bumps.
However, the aforementioned layering method comprises separate steps of forming wires on the semiconductor chip of the wafer and layering another semiconductor chip to be implemented on the semiconductor chip of the wafer. This makes the fabrication process complicated, resulting in an increase in turnaround time and in manufacturing costs. It is also necessary to apply a pressure at high temperatures to both the semiconductor chips when bonded together. This in turn causes the pressure to be exerted on the wire or circuit underlying the terminal of the chip, possibly leading to degradation in transmission characteristics due to a break or distortion in the wire. In particular, these disadvantages conceivably appear when a porous insulating material, the demand for which will grow increasingly, is used as an interlayer insulating film for wires within the semiconductor element.
The present invention was developed in view of the aforementioned problems. It is therefore an object of the present invention to provide a semiconductor device having semiconductor chips stacked in layers and a method for fabricating the semiconductor device. The highly reliable semiconductor device provides a simplified manufacturing process and a reduced turnaround time, thereby reducing costs and easily ensuring prevention of breaks in wires and improvement in transmission characteristics.
As a result of intensive studies, the present inventor has reached the following embodiments of the invention as described below.
The invention is directed to a semiconductor device having a composite structure with a first semiconductor chip being bonded to a second semiconductor chip.
The semiconductor device according to the invention includes a single electrically conductive film that electrically connects between the first semiconductor chip and the second semiconductor chip and extends on the element-formed surface of the first semiconductor chip.
The method for fabricating a semiconductor device according to the invention includes the steps of: temporarily fixing a first semiconductor chip and a second semiconductor chip with their element-formed surfaces being placed opposite to each other; and forming a single electrically conductive film that electrically connects between the first semiconductor chip and the second semiconductor chip and extends on the element-formed surface of the first semiconductor chip.
For example, it is preferable to employ a plating method to form the electrically conductive film with the first semiconductor chip and the second semiconductor chip being temporarily fixed and thereby retained relative to each other without applying a pressure therebetween.